Silicon Epi Wafer Market

Siltronic shut its SD line in Burghausen during 2025 and stopped making epitaxial and polished wafers of up to 150 mm there, a choice its 12 March 2026 annual results say cost about one third of the year’s sales shortfall. The silicon epi wafer market covers silicon wafers that carry a grown single-crystal silicon layer of controlled thickness and doping, sold to chipmakers for logic, power, analog, image sensor and memory devices. Douglas Insights sizes it at USD 2.27 billion for 2025, built as 17.29 million 300 mm-equivalent epi wafers times an average USD 131.4 per wafer, and projects USD 4.42 billion by 2035 at a revenue CAGR of 6.88%. Older 150 mm lines are closing while 300 mm epi for AI logic keeps reactors full. The study belongs to our single crystal substrates coverage and follows the Douglas Insights research methodology.

How is a silicon epi wafer different from a polished prime wafer?

About 14.6% of 2025 silicon wafer area, by our estimate, shipped as silicon epi wafers. Each is a polished substrate with a deposited silicon film, typically 1 to 25 micrometres thick for integrated circuits, doped differently from the substrate. Buyers pay a premium for that film.

A polished prime wafer is sliced, lapped and polished from a Czochralski crystal. A silicon epi wafer adds one more step in a chemical vapour deposition (CVD) reactor at about 1,100 degrees Celsius, where trichlorosilane or dichlorosilane grows a defect-poor layer. Logic makers use a thin, lightly doped layer on a heavily doped substrate to suppress latch-up. Power device makers want the opposite: thick, lightly doped drift layers above 25 micrometres. The report counts 300 mm, 200 mm, 150 mm and below, and both single-wafer reactors and batch reactors. Silicon carbide and gallium nitride epitaxy are excluded; only silicon on silicon (homoepitaxy) is counted.

Which suppliers control silicon epi wafer reactors and long-term agreements?

Five suppliers hold about 88.6% of silicon epi wafer revenue in 2025, Douglas Insights estimates, led by Shin-Etsu Handotai with a 27.4% share. The basis is disclosed wafer sales, 300 mm epi reactor counts and long-term agreements (LTAs) that lock in volumes with logic foundries.

Shin-Etsu Handotai sits inside Shin-Etsu Chemical, whose group net sales reached JPY 2.56 trillion in fiscal 2024; that balance sheet funds crystal pullers no rival matches. SUMCO reported 2025 sales of JPY 409.6 billion and a 27.4% EBITDA margin on its investor relations page, with a net loss of JPY 11.7 billion as depreciation on new 300 mm capacity landed. Our share figures are estimates, anchored on those disclosures.

GlobalWafers is the most mobile of the five. Its news page lists the 14 September 2026 partial restart of its Novara site in Italy, where epi operations came back first and shipments began, and the 23 September 2026 pricing of a USD 1.43 billion depositary share offering. Siltronic reported 2025 sales of EUR 1.35 billion and capital spending of EUR 369.1 million, much of it for Singapore. SK siltron earned 2.08 trillion won in revenue, with over 50% of sales going to Samsung Electronics and SK hynix, and Doosan has agreed to buy a 70.6% stake. Okmetic, in Vantaa, Finland, is investing nearly EUR 400 million in a 200 mm fab for MEMS, sensor, RF and power wafers.

The top three, Shin-Etsu Handotai, SUMCO and GlobalWafers, hold a combined 65.7% of silicon epi wafer value. Chinese makers such as National Silicon Industry Group are qualifying 300 mm epi at domestic foundries, but leading-node logic epi still comes almost entirely from the five incumbents. Buyers studying the upstream tools can read our Semiconductor Silicon Wafer Polishing Machines Market report.

Which application segment makes the money in silicon epi wafers?

Logic and foundry wafers carry 41.7% of silicon epi wafer value, or USD 947.4 million in 2025, because every leading-edge CMOS logic start at 300 mm uses an epi substrate. CMOS image sensors are the fastest climbers at 6.43% a year, Douglas Insights calculates, as stacked sensors multiply in phones and cars.

Logic and foundry, at USD 947.4 million, grows 8.43% a year to USD 2.13 billion in 2035 because gate-all-around transistors below 3 nm need epi stacks with tighter thickness control. Power and discrete devices take USD 536.2 million, a 23.6% share built on thick drift layers for insulated-gate bipolar transistors (IGBTs) and power MOSFETs; inventory overhang slows that line to 6.25%. Analog and mixed-signal holds USD 361.2 million, or 15.9%, mostly on 200 mm wafers in automotive and industrial controllers. CMOS image sensors hold USD 256.7 million, an 11.3% share, and expand fastest at 6.43% because stacked sensors use two or three wafers each and camera counts per car keep rising. Memory and other uses make up USD 170.4 million at 7.5%; most DRAM and NAND runs on polished wafers, so epi growth there stays near 3.37%.

By diameter, 300 mm epi earns about 78.6% of revenue, 200 mm 17.9% and 150 mm and below 3.5%. Siltronic’s Burghausen exit is the clearest sign that the smallest diameter is shrinking.

Why is AI logic lifting silicon epitaxial layer volumes so fast?

Silicon epi wafer volume grows 5.35% a year to 2035, and AI logic alone adds 2.41 points of that. SEMI said 2025 wafer growth came from strong demand for advanced epitaxial wafers in logic, while the rest of the market stayed soft. Four drivers make up the full volume leg.

AI accelerators and sub-3 nm logic

SEMI’s annual wafer report of 10 February 2026 counted 12.97 billion square inches shipped in 2025, up 5.8%, while revenue fell 1.2% to USD 11.4 billion. Epitaxial wafers for logic and polished wafers for high-bandwidth memory carried the gain. Douglas Insights puts the AI logic driver at 2.41 points of volume growth, because each accelerator die needs a 300 mm epi start and advanced packages consume more wafer area per working chip. Yield losses at 2 nm add starts too. HBM stacks matter as well: SEMI tied polished wafer gains to high-bandwidth memory, and every HBM stack sits beside an accelerator die built on an epi substrate, so the two wafer types now rise together.

Power devices for vehicles and grids

Power conversion contributes 1.37 points. Every battery electric car carries silicon IGBTs or superjunction MOSFETs in its on-board charger and auxiliary inverters, even when the traction inverter moves to silicon carbide. Grid storage, solar inverters and data-centre power supplies add steady 200 mm epi orders. Thick drift layers of 40 to 120 micrometres take three to five times the reactor hours of a thin logic layer, so each power wafer absorbs more capacity than its count suggests. Siltronic still named high power-segment inventories as a 2025 drag, which is why we hold this driver below its long-run pace until destocking ends.

New fabs outside Taiwan and Japan

Fab construction adds 0.94 points. GlobalWafers’ Texas plant, Siltronic’s Singapore fab, which began depreciation from August 2025, and Okmetic’s 200 mm expansion in Finland each create a local silicon epi wafer source that foundries qualify before ramping. Qualification itself burns wafers: a new epi source typically needs 6 to 12 months of test lots.

Image sensors and analog chips

The last 0.63 points come from image sensors and analog. Cameras per car rise and smartphone sensors move to stacked designs with two or three wafers per sensor. The four drivers add to 5.35 points, which is the volume leg before price.

Which bottlenecks slow silicon epi reactor capacity and power-device orders?

Three restraints take 1.18 points off silicon epi wafer volume growth, already netted out of the 5.35% leg: power-device inventory, reactor and part lead times, and 150 mm line closures. Without them, volume would rise near 6.53% a year.

Power inventory removes 0.52 points. Siltronic said high inventories in the power segment and a weak US dollar dampened its 2025 sales, which fell to EUR 1.35 billion from EUR 1.41 billion. Distributors holding six months of IGBT stock defer epi orders until it clears.

Reactor supply removes 0.41 points. A single-wafer epi chamber, graphite susceptors and high-purity trichlorosilane all come from a short list of vendors, and new chambers can take 9 to 14 months to arrive and qualify. Our Semiconductor Wafer Handling Robots Market study tracks the automation that has to arrive alongside them.

Closures of small-diameter lines remove 0.25 points. The Burghausen SD exit pulls 150 mm epi supply from the market faster than customers redesign onto 200 mm, and some discrete and sensor buyers will simply stop ordering.

Where are the silicon epi wafer lines, from Hsinchu to Sherman?

Asia Pacific buys USD 1.42 billion of silicon epi wafers in 2025, the largest regional pool, because Taiwan, South Korea, Japan and China host most 300 mm logic, image sensor and memory fabs. The Middle East and Africa grows fastest at 9.86% from a small base.

Douglas Insights expects Asia Pacific to reach USD 2.85 billion by 2035, rising 7.24% a year as Taiwanese foundries and Chinese fabs expand. North America takes USD 359.0 million in 2025 and grows 7.12% to USD 714.2 million, helped by GlobalWafers’ Sherman plant and new US logic fabs. Europe holds USD 395.3 million and grows slowest at 4.93%, as power and automotive analog dominate its mix and 150 mm lines close. The Middle East and Africa, at USD 47.7 million, is the fastest-growing region because a handful of new 300 mm device lines lift a small base. Latin America is the wildcard at USD 54.5 million and 5.70% a year: almost no wafer fabrication exists there today, so a single fab decision in Mexico or Brazil would change the figure.

How much does a 300 mm silicon epi wafer cost against a polished one?

A 300 mm silicon epi wafer for logic sells for about USD 150 to USD 215 in 2025, Douglas Insights finds. SEMI data imply an all-wafer average of USD 96.3 per 300 mm equivalent. Our blended epi price of USD 131.4 sits 36.5% above that average.

Pricing splits by diameter. A 200 mm epi wafer for power or analog sells for about USD 58 to USD 84, and a 150 mm wafer for USD 27 to USD 41. Thick power layers cost more per wafer because reactor time rises with thickness. Most 300 mm volume moves under multi-year LTAs with fixed prices, and Siltronic cites price effects outside those agreements; spot prices outside those contracts fell in 2025, which is why SEMI revenue dropped while area rose. Douglas Insights expects the blended price to rise 1.45% a year to USD 151.7 by 2035 as the mix moves to 300 mm and thicker multi-layer stacks.

Which standards and CHIPS rules shape silicon epi wafer supply?

SEMI M62, revised as M62-1125 in November 2025, sets the specification for silicon epi wafers, while CHIPS Act grants of up to USD 406 million to GlobalWafers fund new US wafer capacity. Together they set the quality bar and the location of new supply.

The SEMI M62 standard covers silicon homoepitaxial layers: discrete-device wafers with layers thicker than 25 micrometres, and integrated-circuit wafers of 100 mm or larger with layers up to 25 micrometres. It fixes limits for thickness variation, carrier density, resistivity, flatness and localized light scatterers, and draws on more than 20 other SEMI test methods. Buyers write their incoming checks against it.

On 17 December 2024 the US Commerce Department finalised CHIPS awards of up to USD 406 million for GlobalWafers. The Sherman, Texas plant will make the first US 300 mm silicon wafers for advanced chips and convert existing epi capacity to silicon carbide; St. Peters, Missouri adds 300 mm silicon-on-insulator wafers. The projects carry about USD 4 billion of capital spending and 880 manufacturing jobs.

What if power-device inventories linger: how far apart are the 2035 silicon epi wafer cases?

The base case reaches USD 4.42 billion in 2035, with 5.35% volume and 1.45% price growth a year. A slower case, with power inventory lasting into 2028, ends near USD 3.44 billion; a faster case, with AI logic starts doubling, reaches USD 5.66 billion.

Sensitivity is high. One extra point of annual volume growth adds about USD 437.8 million to the 2035 silicon epi wafer value. The fastest swing factor is the Novara and Burghausen pattern: GlobalWafers’ Italian restart and Siltronic’s 150 mm exit show how one site decision moves regional supply. Published forecasts run from about 4.8% to 13.3% a year; our 6.88% sits in the lower half, because we strip silicon carbide out of the count.

Douglas Exclusive: the Epi Capacity Calendar

The Epi Capacity Calendar is a Douglas Insights model built from 11 dated capacity and policy events and 9 sourced numeric inputs. It places each silicon epi wafer supply change on a month line from 2024 to 2027, and it is our own count, not an official register.

The calendar finds that between June 2024 and September 2026 five of the 11 events added or restored silicon epi wafer capacity, three removed or paused it, and three changed funding, ownership or specification. Net additions arrive mostly at 300 mm in Asia and the US, while removals are concentrated in European 150 mm and 200 mm lines. Siltronic cut its 2026 capital spending guidance to EUR 180 to 220 million from EUR 369.1 million in 2025, a sign that the next capacity wave is at least 18 months away.

How quickly does 200 mm silicon epi fade against 300 mm?

The 300 mm share of silicon epi wafer revenue rises from 78.6% in 2025 to about 84.2% by 2035, by our model. Over the same decade 200 mm slips to roughly 14.1%, and 150 mm and below shrinks below 2%. Power and analog keep 200 mm alive.

The fade is slow. Automotive qualification cycles of five to seven years mean a controller designed on 200 mm epi in 2024 will still ship in 2031. Okmetic’s new Vantaa fab and 200 mm electrostatic chucks still being sold, covered in our 200mm Wafer Used Electrostatic Chuck Market report, show that the diameter keeps getting investment.

Methodology: how did we count silicon epi wafers in 300 mm equivalents?

The model starts from SEMI’s 12.97 billion square inches of 2025 silicon wafer shipments, converts them at 109.6 square inches per 300 mm wafer into 118.4 million equivalents, and assigns 14.6% to epi. That yields 17.29 million epi wafers.

Arithmetic: 17.29 million wafers times USD 131.4 equals USD 2.27 billion. Five regions and 12 wafer-producing countries are modelled from 9 sourced inputs: SEMI totals, five company disclosures, one standard and two policy records. Cross-check one: our silicon epi wafer value equals 19.9% of SEMI’s USD 11.4 billion wafer revenue on 14.6% of area, which matches the 36.5% price premium. Cross-check two: the five application segments sum to USD 4.42 billion in 2035, within 0.1% of the top-down figure. Volume reaches 29.12 million wafers in 2035.

Sources

1. Siltronic AG Siltronic 2025 results press release (2026)
2. SEMI 2025 annual worldwide silicon wafer shipments and revenue (2026)
3. NIST, US Department of Commerce CHIPS incentives awards to GlobalWafers (2024)
4. SEMI SEMI M62 Specification for Silicon Epitaxial Wafers (2025)
5. GlobalWafers GlobalWafers news (2026)
6. SUMCO SUMCO investor relations (2026)

What should a fab buyer lock into silicon epi wafer contracts before 2027?

Fab buyers should secure 300 mm silicon epi wafer volume under LTAs before 2027, when Douglas Insights expects logic epi demand to absorb the Singapore and Texas capacity now ramping. Second-source qualification takes 6 to 12 months.

Three clauses matter most. A dual-site clause protects against events like the July 2026 Novara fire, after which GlobalWafers restarted epi first. A thickness-tier price grid keeps thick power layers from being priced as logic. A SEMI M62 reference clause keeps incoming inspection consistent across suppliers. Expect 2026 to land near USD 2.43 billion.